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NXP Semiconductors /LPC13xx /PMU /PCON

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Interpret as PCON

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)RESERVED 0 (SLEEP_DEEPSLEEP)DPDEN 0 (RESERVED)RESERVED0 (NO_POWER_DOWN_)SLEEPFLAG 0 (RESERVED)RESERVED 0 (NO_DEEPPOWERDOWN)DPDFLAG 0 (RESERVED)RESERVED

DPDFLAG=NO_DEEPPOWERDOWN, SLEEPFLAG=NO_POWER_DOWN_, DPDEN=SLEEP_DEEPSLEEP

Description

Power control register

Fields

RESERVED

Reserved. Do not write 1 to this bit.
DPDEN

Deep power-down mode enable

0 (SLEEP_DEEPSLEEP): ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M3 core turned off).

1 (DEEPPOWERDOWN): ARM WFI will enter Deep-power down mode (ARM Cortex-M3 core powered-down).
RESERVED

Reserved. Do not write ones to this bit.
SLEEPFLAG

Sleep mode flag

0 (NO_POWER_DOWN_): Read: No power-down mode entered. LPC13xx is in Run mode. Write: No effect.

1 (POWERDOWN): Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
RESERVED

Reserved. Do not write ones to this bit.
DPDFLAG

Deep power-down flag

0 (NO_DEEPPOWERDOWN): Read: Deep power-down mode not entered. Write: No effect.

1 (DEEPPOWERDOWN): Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
RESERVED

Reserved. Do not write ones to this bit.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data